1. Field of the Invention
The present invention relates to a method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. Moreover, pursuant to the invention, there is provided a z-interconnected dielectric layer structure produced by the method as described herein, employing dielectric materials, such as resin coated copper, of the type supplied by Isola Laminates as “RCC” or a polymer coated copper such as supplied by Asahi, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.
Currently, in the industry which is concerned with the manufacture of electronic packages, such as those including printed wiring boards, resin coated copper materials are employed in the processing of built-up dielectric layers which may provide for z-interconnections upon lamination and the provision of vias therein. Generally, the resin coated copper material is applied to the printed wiring board, thereafter fully cured, vias are then formed, plating is implemented as required and then circuitized, and is well known in the technology. However, the materials which are employed, such as the resin coated copper, in effect, a filled polyphenylene ether (PPE) coated copper, such as sold by Asahi as APPE, is subject to a deficiency which resides in that in its uncured state the material cannot be wet processed or, alternatively, is incapable of being fully cured and bonded.
2. Discussion of the Prior Art
Although various publications are currently disclosed in the technology, and which are intended to form generally small pitch z-interconnections, none of these are applicable to the present invention.
Cole, Jr. et al. U.S. Pat. No. 5,745,984 discloses a method for producing an electronic module which incorporates a high density interconnect structure employing a KAPTON® layer as a redistribution layer. This has nothing in common with the present invention and it does not employ a resin coated copper material (RCC) analogous to that provided herein in forming the small pitch z-interconnections.
Jiang, et al. U.S. Pat. No. 6,163,957 discloses a multi-layered substrate with high density interconnects and methods of making the same, wherein circuitized pads are employed for the interconnect area. In lieu of having through vias or blind vias, a via is drilled through a substrate to a pad on the other side thereof, terminating on a pad at a first surface of a first circuit layer. This is completely different from the present invention and has nothing in common therewith.
Haas et al. U.S. Pat. No. 6,245,696 B1 discloses a lasable bond-ply material which is employed in the construction of multi-layer wiring boards. The material is B-staged, and various embodiments as disclosed therein provide for a laser drilling of vias and filling thereof with a conductive ink, and then forming a laminated structure. Although, in general, this is somewhat similar to the present invention, unlike this publication the present invention disclosure employs a resin-coated copper (RCC), whereas in contrast therewith, the patent discloses a mixture of a micro-fiberglass and fibers forming a different prepreg material which is intended to be laminated. Consequently, both as to method and structure, the Haas et al. patent is completely different from the present invention as disclosed and claimed herein.
Finally, Ochi, et al. Patent Appln. Publication No. U.S. 2002/0023777A1 employ a base member which is constituted of two materials, whereas contrastingly, the present invention utilizes a single material of greater simplicity and economical nature.